HDLBits-Karnaugh Map to Circuit
Problem 72 3-variable
The circuit is realized according to the Karnaugh diagram, and the circuit design is completed in the form of the sum of the product of the maximum term and the minimum term. Before writing verilog, you can simplify the Karnaugh map.
Posted by keyont on Mon, 06 Dec 2021 13:14:49 -0800
The book continues from the above. The previous article introduced the slightly simple synchronous fifo, and then began the more complex asynchronous fifo.
1. Difference between synchronous fifo and asynchronous fifo
When there is only one clock in the design, whether all registers use the same one, there will be no transmission speed ...
Posted by Sooz719 on Tue, 30 Nov 2021 12:26:46 -0800
UVM register model integration
The bus interface timing of MCDF access register is relatively simple. The control register interface first needs to parse cmd at each clock. When cmd is a write instruction, you need to cmd the data_ data_ Write in to cmd_ In the register corresponding to addr. When cmd is a read instruction, you need to rea ...
Posted by sonny on Mon, 22 Nov 2021 18:34:45 -0800
UVM layering sequence
Introduction to layering sequence
If we are building more complex protocol bus transmission, such as PCIe, USB3.0, etc., a single transmission level will be less friendly to future incentive multiplexing and upper layer control. For this deeper data transmission, in practice, both VIP and self-developed environments ...
Posted by whizkid on Sat, 20 Nov 2021 17:40:41 -0800
UVM message management
A good verification system should have message management features, which are:
Print information in a standardized wayFilter (importance level) informationPrint channel These features are supported in UVM, which provides a series of rich classes and methods to generate and filter messages:Message method ...
Posted by fitchn on Thu, 11 Nov 2021 18:57:34 -0800
A program in a class is also called a method, that is, an internal task or function defined within the scope of the class. The following example defines the display () method for the Transaction class. System Verilog will call the correct display () method according to the type of handle.
Posted by slands10 on Mon, 08 Nov 2021 02:38:44 -0800
2.2.2Vectors in more detail(Vector1)
A Bit of Practice:
2.2.3Vector part select(Vector2)
2.2.6Vector concatenation operator(Vector3)
A Bit of Practice:
Posted by fanfavorite on Sun, 07 Nov 2021 10:02:32 -0800
As long as all the modules used belong to the same project, you can create a hierarchy of modules by instantiating them within the module. Two ways are to connect by location and name, Adjust by position (concise but unstable, no messy order), by name (variable order) By location: mod_a instance1 (wa, wb, wc) By name: mod_ A ins ...
Posted by xeirus on Wed, 20 Oct 2021 10:17:25 -0700
Discovery phase interaction process
PPPoE (point to point protocol over Ethernet) is a point-to-point protocol based on Ethernet, including discovery phase and session phase. The discovery phase, PPPoE Discovery, aims to obtain the client MAC address and establish a connection. The discovery stage includes PADI, PADO, PADR and PADS. After ...
Posted by Alex-B on Thu, 14 Oct 2021 12:30:56 -0700