Verilog on-board experiment: multifunctional counter

catalog Experimental requirements Step 1: A add and subtract counter is designed, which is combined with binary to BCD decoder and alternating display control circuit in Experiment 1 As shown in the figure: Counter input: Clk,Up,Down,Rst,Enable 8bits output: Cnt7~Cnt0 Rst=1, the counter is cleared ...

Posted by bapan on Sun, 28 Jun 2020 21:43:02 -0700

Verilog Preliminary Tutorial Verilog Modules and Ports

Bowen catalog Write before text Modular port port type Verilog 1995 vs. Verilog 2001 Reference material Make a friend Write before The first five articles have already explained Verilog's bits and pieces of knowledge, starting with modules. Modular design is the core of Verilog and digital ...

Posted by newzub on Fri, 26 Jun 2020 18:18:05 -0700

Verilog Simple Design for Seven Segments of Digital Tube Display

Bowen catalog Write before text Principle of seven-segment digital tube Seven Segments Digital Tube Decoder Table verilog design for single seven-segment digital tube display Dynamic Scan Display with Multiple Digital Tubes Reference material Make a friend Write before As a basic knowledge tu ...

Posted by cjliu42 on Sat, 20 Jun 2020 17:56:21 -0700

Minimalist tutorial on basic knowledge of field programmer

Bowen catalog Write before text FIFO in GA/ASIC Design of synchronous FIFO Reference material Make a friend Write before Personal Blog Home Page Note: Learn to communicate! text FIFO in GA/ASIC How FIFO buffers are used to transfer data and across clock domains The abbreviation FIFO s ...

Posted by moty66 on Sun, 07 Jun 2020 18:50:08 -0700

An example of getting started with ZYNQ -- timer interruption and program solidification

I. Preface In the APU system, the CPU performs the operation in the way of serial code execution, and the software mode is difficult to achieve accurate timing, so it is a better choice to call the internal timer hardware to complete timing. In this paper, timer interrupt control LED periodic flicker as an example to learn the use of private ti ...

Posted by shumway on Sun, 08 Mar 2020 04:30:32 -0700

System Verilog builds APB ﹣ I2C IP hierarchical verification platform

I. Preface Recently, the epidemic is serious. As a social animal, I can only continue to study technology at home. I wrote a blog about building a FIFO verification platform before, using the OOP feature of SV to preliminarily verify FIFO, but there are many shortcomings, such as the structure is not standardized, the verification component cla ...

Posted by PupChow on Fri, 07 Feb 2020 09:10:51 -0800

Understand the structure and working principle of CPU in the code

I. Preface From the beginning of graduate school to half a year's work, I have been contacting MCU SOC controllers with CPU as the core, but because of professional reasons, I have no idea about the internal structure and working principle of CPU. Today, I broke the blind spot from a blog. It is hereby declared that the design idea and code of ...

Posted by cottonbuds2005 on Mon, 03 Feb 2020 01:53:57 -0800

[GA]Verilog 60s stopwatch timer (maximum timetable up to 9 min)

[GA]Verilog 60s stopwatch timer 1. Citation This experiment is based on an optional topic during my undergraduate course Number of Junctions.Since the upload was post-perception and the school had recycled the toe plates, it was impossible to post an effect picture of the code results in this article, but the final effect has been tested and ca ...

Posted by kruahsohr on Sun, 15 Dec 2019 00:44:15 -0800

Open square verilog code

Catalog 1. Description of successive approximation algorithm 2.Verilog implementation 3. Written ...

Posted by doox00 on Fri, 25 Oct 2019 07:37:15 -0700

# Jiangxi CCPC Provincial Competition-Rng (Probability+Inverse Element)

Jiangxi CCPC Provincial Competition-Rng (Probability+Inverse Element) Title: Given an n, choose a R1 between [1,n], choose an L1 between [1,R1], get an interval [L1,R1], get an interval [L2,R2], and ask the probability of intersection of two intervals to model 1e9+7. Train of thought 1: Discuss in different situations, the use of conditional ...

Posted by kashmirekat on Mon, 14 Oct 2019 12:35:53 -0700