After brushing this set of questions, I found that Verilog is so simple - HDLBits answer series

Keywords: Verilog FPGA Hdlbits

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Write in front

Write a new pit: recommend a very good website for practicing Verilog. There are one or two hundred questions, which basically covers all aspects of Verilog grammar. It is a very good introductory learning website. Website connection: HDLBits

The questions are all done by ourselves. They are the correct answers that have been verified. By the way, their own ideas for solving problems are attached. Each topic only lists one method, but I know that many topics have many solutions, and the time relationship is not listed one by one. Hope to help you.

1,Getting Started

1.1,Getting Started

Personal thoughts:

        Just make the output constant to 1.

module top_module( 
    output one 
);

assign one = 1'b1;    //The output is constant to 1

endmodule

1.2,Output Zero

Personal thoughts:

        Just make the output constant to 0.

module top_module(
    output zero
);

    assign zero = 1'b0;       //The output is 0

endmodule

2,Verilog Language

2.1,Basics

2.1.1,Simple Wire

Personal thoughts:

        It mainly investigates the use of assign statement to make the output equal to the input.

module top_module( input in, output out );

    assign out = in;        //Output equals input

endmodule

2.1.2,four wires

Personal thoughts:

         Mainly investigate the use of the assign statement, and output the input of the response according to the corresponding relationship of the picture.

module top_module( 
    input a,b,c,
    output w,x,y,z );

    assign w = a;
    assign x = b;
    assign y = b;
    assign z = c;

endmodule

2.1.3,Invert 

Personal thoughts:

         This paper mainly investigates the application of non gate. The output is equal to the input and can be reversed.

module top_module( input in, output out );

    assign out = ~in;

endmodule

2.1.4,AND Gate

Personal thoughts:

         It mainly investigates the application of and gate. The output is equal to the sum of two inputs.

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = a & b;
    
endmodule

2.1.5,NOR Gate

Personal thoughts:

         It mainly investigates the application of NOR gate. The output is equal to the opposite of the sum of two inputs.

module top_module( 
    input a, 
    input b, 
    output out );

    assign out = ~(a | b);
    
endmodule

2.1.6,Xnor gate 

Personal thoughts:

         This paper mainly investigates the application of the same or gate (XOR not gate). The output is equal to two inputs, and the XOR can be reversed.

module top_module( 
    input a, 
    input b, 
    output out );
    
    assign out = ~(a ^ b);
    
endmodule

2.1.7,Declaring wires 

Personal thoughts:

         It is mainly the declaration of wire type and the use in combination with the assign statement.

         Declare the corresponding wire variable according to the picture and operate it with the corresponding logical operator.

module top_module(
    input a,
    input b,
    input c,
    input d,
    output out,
    output out_n   ); 

    wire ab;
    wire cd;
    wire abcd;
    
    assign ab = a & b; 
    assign cd = c & d;
    assign abcd = ab | cd;
    assign out = abcd;
    assign out_n = ~abcd;
    
endmodule

2.1.8,7458 Chip

Personal thoughts:

         It is mainly the declaration of wire type and the use of assign statement. The picture shows the logic functions realized by 7458 chip.

         Declare the corresponding wire variable according to the picture and operate it with the corresponding logical operator.

module top_module ( 
    input p1a, p1b, p1c, p1d, p1e, p1f,
    output p1y,
    input p2a, p2b, p2c, p2d,
    output p2y );

    assign p1y = (p1a & p1b & p1c) | (p1f & p1e & p1d);
    assign p2y = (p2a & p2b) | (p2c & p2d);
    
endmodule

2.2,Vectors

2.2.1,Vectors

Personal thoughts:

         It is mainly the use of vector type variables combined with assign statements, as well as the bit operation of vector type variables.

         Use the assign statement to assign values according to the corresponding images.

module top_module ( 
    input wire [2:0] vec,
    output wire [2:0] outv,
    output wire o2,
    output wire o1,
    output wire o0  ); 

    assign outv = vec;
    assign o2 = vec[2];
    assign o1 = vec[1];
    assign o0 = vec[0];
    
endmodule

2.2.2,Vectors in more details

Personal thoughts:

         It is mainly the use of vector type variables combined with assign statements, as well as the bit operation of vector type variables.

        Assign the upper 8 bits of the input to out_hi; The lower 8 bits are assigned to out_lo.

module top_module( 
    input wire [15:0] in,
    output wire [7:0] out_hi,
    output wire [7:0] out_lo );

    assign	out_hi = in[15:8];
    assign	out_lo = in[7:0];
    
endmodule

2.2.3, Vectors part select

Personal thoughts:

        The 32-bit input is regarded as a combination of four 8-bit data.

        Exchange the highest 8-bit data with the lowest 8-bit data, and the second highest 8-bit data with the second lowest 8-bit data.

module top_module( 
    input [31:0] in,
    output [31:0] out );

    assign out[31:24] = in[7:0];
    assign out[23:16] = in[15:8];
    assign out[15:8] = in[23:16];
    assign out[7:0] = in[31:24];
    
endmodule

2.2.4,Bitwise operations

Personal thoughts:

        It mainly investigates bit operations and logical operations, such as bitwise and, logical and, etc.

         out_or_bitwise is two input bitwise OR; out_or_logical is two input logical or; out_not means that two inputs are spliced together after being reversed bit by bit (the order here should be arbitrary, but the author sets input b first)

module top_module( 
    input [2:0] a,
    input [2:0] b,
    output [2:0] out_or_bitwise,
    output out_or_logical,
    output [5:0] out_not
);
    assign out_or_bitwise = a | b;
    assign out_or_logical = a || b;
    assign out_not = {~b,~a};

endmodule

2.2.5,Four-input gates

Personal thoughts:

        For an input signal with a bit width of 4, each bit can be bit and, bit or, bit XOR.

module top_module( 
    input [3:0] in,
    output out_and,
    output out_or,
    output out_xor
);
    assign out_and = in[3] & in[2] & in[1] & in[0]; 
    assign out_or  = in[3] | in[2] | in[1] | in[0];
    assign out_xor = in[3] ^ in[2] ^ in[1] ^ in[0];
    
endmodule

2.2.6,Vector concatenation operator

Personal thoughts:

        This paper mainly investigates the use of bit splicing operators.

        According to the corresponding relationship given in the picture, use the bit splicing operator to splice.

module top_module (
    input [4:0] a, b, c, d, e, f,
    output [7:0] w, x, y, z );//

    assign z = { e[0],f,2'b11};
    assign y = { d[3:0],e[4:1]};
    assign x = { b[1:0],c,d[4]};
    assign w = { a,b[4:2]};

endmodule

2.2.7,Vector reversal

Personal thoughts:

        Invert the 8-bit input to output, and you can use the bit splicing operator to splice bit by bit.

module top_module( 
    input [7:0] in,
    output [7:0] out
);
    assign out = {in[0],in[1],in[2],in[3],in[4],in[5],in[6],in[7]};
    
endmodule

2.2.8,Replication operator 

Personal thoughts:

        This paper mainly investigates the use of bit extension operators. The bit expansion operator is similar to the bit splicing operator and is suitable for splicing duplicate data.

        The high 24 bits of the output are all changed to the highest bit of the input in, and then spliced together.

module top_module (
    input [7:0] in,
    output [31:0] out );//

    assign out = { {24{in[7]}},in };

endmodule

2.2.9,More Replication

Personal thoughts:

        The output can be regarded as a NOR gate with two inputs.

        One input is spliced by 5 abcde s; The other input is spliced by 5 a, 5 b, 5 c, 5 d and 5 e.

module top_module (
    input a, b, c, d, e,
    output [24:0] out );//

    assign out = {5{a,b,c,d,e}} ~^ {{5{a}},{5{b}},{5{c}},{5{d}},{5{e}},};
    
endmodule

        

Posted by nafarius1357 on Wed, 01 Sep 2021 21:35:04 -0700