System Verilog OOP: encapsulation, inheritance, and polymorphism
1. Three basic characteristics of object-oriented
Object: everything is an object Class: a class is an abstract collection of objects with the same properties and behavior Instance: an object is an instance of a class Encapsulation can hide the implementation details and make the code modular; Inheritance can extend existing code modules, ...
Posted by 9911782 on Mon, 06 Dec 2021 12:16:05 -0800
(25)UVM register model integration
UVM register model integration
The bus interface timing of MCDF access register is relatively simple. The control register interface first needs to parse cmd at each clock. When cmd is a write instruction, you need to cmd the data_ data_ Write in to cmd_ In the register corresponding to addr. When cmd is a read instruction, you need to rea ...
Posted by sonny on Mon, 22 Nov 2021 18:34:45 -0800
(23) layering sequence of UVM
UVM layering sequence
Introduction to layering sequence
If we are building more complex protocol bus transmission, such as PCIe, USB3.0, etc., a single transmission level will be less friendly to future incentive multiplexing and upper layer control. For this deeper data transmission, in practice, both VIP and self-developed environments ...
Posted by whizkid on Sat, 20 Nov 2021 17:40:41 -0800
UVM message management
UVM message management
1, Foreword
A good verification system should have message management features, which are:
Print information in a standardized wayFilter (importance level) informationPrint channel These features are supported in UVM, which provides a series of rich classes and methods to generate and filter messages:Message method ...
Posted by fitchn on Thu, 11 Nov 2021 18:57:34 -0800
system verilog object oriented programming
Class method
A program in a class is also called a method, that is, an internal task or function defined within the scope of the class. The following example defines the display () method for the Transaction class. System Verilog will call the correct display () method according to the type of handle.
class Transaction;
bit[31:0]addr,crc ...
Posted by slands10 on Mon, 08 Nov 2021 02:38:44 -0800
Definition of function and task (systemverilog)
There are two methods defined in sv's class:.function and task.Below are descriptions of their features and ways of declaring them, as well as their similarities and differences.
1. function
Features of 1.1 function
function cannot have built-in time-consuming statements, which are returned immediately upon invocation, i.e. do not consum ...
Posted by argoSquirrel on Fri, 03 Sep 2021 18:38:19 -0700