Small Problems of VGA Display Pictures Based on FPGA Driver

Keywords: Verilog

In the process of learning VGA to display pictures, I encountered a small problem. I opened a 60x60 box on the display screen and put a picture in it, but the final result is shown in the following figure.

There is a vertical black edge, look at the code, analyze the logic is no problem, but look at this display that must be a problem, and then simulate a look, the sequence diagram is as follows.

Correct timing

Error timing

This is when the line counter is recorded to 200 and the field counter is recorded to 200, the data in the ROM is displayed, and a square display area of 60x60 is opened in the display screen. Comparing the two pictures above, the second one is that when the line counter is counted to 200, the lcd_data should be the data in the ROM, but the output is 16'h00. This is because my original code is written as follows: When the line counter records 200, add 1 to the ROM address, and then an enabling signal reads out the output of the ROM. But in fact, when the line counter records 200, the ROM address has been added 1, then the first data of the ROM can not be read out, and then it is displayed from the second data, that is, the first data of each line is not given, so it will eventually display a vertical black edge. How to solve the problem? Simply, the enabling signal is given when the line counter is recorded to 199, so when the display screen displays 200 data, the first data of ROM reads out exactly. The code is as follows:

 1 //---------------------------------------------
 2 //addra
 3 always @(posedge clk or negedge rst_n)begin
 4     if(!rst_n)
 5         addra <= 16'd0;
 6     else if(addra == 3600 - 1'b1)
 7         addra <= 16'd0;
 8     else if(lcd_x >= 200 && lcd_x < 260 && lcd_y >= 200 && lcd_y < 260)
 9         addra <= addra + 1'b1;
10     else
11         addra <= addra;
12 end
13 
14 //-----------------------------------------------------------------------
15 //pic_en
16 reg     pic_en;
17 always @(posedge clk or negedge rst_n)begin
18     if(!rst_n)
19         pic_en <= 1'b0;
20     else if(lcd_x >= 200 && lcd_x < 260 && lcd_y >= 200 && lcd_y < 260)
21         pic_en <= 1'b1;
22     else 
23         pic_en <= 1'b0;
24 end
25 
26 //-----------------------------------------------------------------------
27 //data_en
28 reg     data_en;
29 always @(posedge clk or negedge rst_n)begin
30     if(!rst_n)
31         data_en <= 1'b0;
32     else if(lcd_x >= 199 && lcd_x < 259 && lcd_y >= 200 && lcd_y < 260)
33         data_en <= 1'b1;
34     else 
35         data_en <= 1'b0;
36 end    
37     
38 //lcd_data    
39 reg     [15:0]    lcd_data_r0;
40 reg     [15:0]    lcd_data_r1;
41     
42 always @(posedge clk or negedge rst_n)begin
43     if(!rst_n)
44         lcd_data_r0 <= 16'b0;
45     else if(lcd_y > 0 && lcd_y <= 150)
46         lcd_data_r0 <= `WHITE;
47     else if(lcd_y > 150 && lcd_y <= 350)
48         lcd_data_r0 <= `GREEN;
49     else if(lcd_y > 350 && lcd_y <= 480)
50         lcd_data_r0 <= `BLUE;
51     else 
52         lcd_data_r0 <= 16'b0;
53 end
54
55 always @(posedge clk or negedge rst_n)begin
56     if(!rst_n)
57         lcd_data_r1 <= 16'b0;
58     else if(pic_en == 1'b1)
59         lcd_data_r1 <= douta;
60     else
61         lcd_data_r1 <= 16'b0;
62 end
63     
64 //assign lcd_data = (pic_en == 1'b1)? `CYAN: lcd_data_r0;//Open a purple box
65 
66 assign lcd_data = (pic_en == 1'b1)? lcd_data_r1: lcd_data_r0;

 

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Original address: http://www.cnblogs.com/ninghechuan/p/7577224.html 

Posted by abakash on Wed, 22 May 2019 16:12:36 -0700