Data FIFO
I. write enable - wr_en, write data - wdata

//din :8bit
assign      wr_en = din_vld ;//din_vld is the effective indication signal of data
assign      wdata = {din_sop,din_eop,din};//If it is in package form, sop and eop can be written into data FIFO to ensure that starting and ending conditions are always synchronized with data

Note: the write enable and write data at the moment are combined logic. If one of them uses sequential logic, based on the principle of synchronization, the other must also be synchronized

always @(posedge clk or negedge rst_n)begin
  if(rst_n==0)begin
       wr_en <= 0;
  end
  else begin
       wr_en <= din_vld;
  end
end

always @(posedge clk or negedge rst_n)begin
  if(rst_n==0)begin
       wdata <= 0;
  end
  else begin
       wdata <= {din_sop,din_eop,din};
  end
end

2. Read enable - Rd UU en, output data - q[7:0]

assign   rd_en = empty == 0;//Data FIFO is not empty
//Show ahead mode is preferred

III. data reading part (including DIN \ u SOP and DIN \ u EOP)

//dout
always@(posedge clk or negedge rst_n)begin
    if(rst_n == 0)begin
       dout <= 0;
    end
    else begin
      dout <= q[7:0];
    end
end 
assign    dout_sop_tmp  = q[9] && rd_en;
assign    dout_eop_tmp = q[8] && rd_en;
//dout_sop
always@(posedge clk or negedge rst_n)begin
    if(rst_n == 0)begin
       dout_sop <= 0;
    end
    else begin
      dout_sop <= dout_sop_tmp;
    end
end
//dout_eop
always@(posedge clk or negedge rst_n)begin
    if(rst_n == 0)begin
       dout_sop <= 0;
    end
    else begin
      dout_sop <= dout_eop_tmp;
    end
end

always @(posedge clk or negedge rst_n)begin
   if(rst_n == 0)begin
      dout_vld <= 0;
   end
   else begin
     dout_vld <= rd_en;
   end
end

Information FIFO
It does not need a lot of storage space, but it is very convenient to tell the data when to read FIFO. For example, it is required to output message when receiving EOP. If the length of the first message is 200 bytes and the length of the second message is less than 200 bytes, if the read enable is set to rd_en = empty = = 0 & & din_eop;
Then the eop of the second message is received when the first message is not output completely. At this time, the next message should be output according to the logic of rd_uen, but obviously the first message is not output completely, which will result in the loss of data.
According to the read-write isolation principle of FIFO, information FIFO is used.
I. write enable and write data

assign     msg_wr_en       =  din_eop ; //Enter a complete message, where the conditions can be changed according to different requirements
assign     msg_wr_wdata =  1 ;//Because it only serves as an identifier, it can store anything. If there is something to store, for example, the message length can be stored in the information FIFO

II. Reading enabling

assign   msg_rd_en  =  msg_empty == 0;//Information FIFO is not empty, indicating that there is at least one complete message in data FIFO