Chapter one: introduction to microcomputer system
1. Which generations are computers divided into according to the different logic elements they use? Which - generation of computers is Microcomputer?
Answer: electronic tube computer, transistor computer, integrated circuit computer and large-scale and super large-scale integrated circuit computer. Microcomputer belongs to the branch of the fourth generation computer.
2. Briefly describe the basic idea of von Neumann's computer architecture.
A: von Neumann's basic design idea is: ① express instructions and data in binary form. ② The program and data are stored in the memory in advance, and the computer can take out instructions from the memory and execute them at high speed. ③ The computer system is composed of five parts: arithmetic unit, controller, memory, input and output equipment.
3. What are the components of microcomputer system:
A: the microcomputer system is divided into hardware and software. The hardware includes CPU, memory, input and output equipment and input and output equipment, and the software includes software system and application software.
6. What is a bus? What kinds are there? How does it work?
A: the bus is a common channel for transmitting information between functional components in the computer. According to the content and function of the transmitted information, the bus can be divided into three categories: address bus, data bus and control bus. These three types of buses are used to transmit address, data and control information among various functional components of the computer.
8. What are the differences between memory read and write operations?
Answer: ① read operation: it is controlled by the read command issued by the CPU. Write operation: controlled by the write command issued by the CPU. ② Read operation: read the data from the memory and put it on the DB. Write operation: put D
B, write to memory.
Chapter two: number system and coding in computer
1. Convert decimal numbers to binary and hexadecimal
(1) 129.75= 1000 0001.11B=81.CH (2) 218.8125 = 1101 1010.1101B =DA.DH (3) 15.625=1111.101B=F.AH (4) 47.15625=10 111.0010 1B=2F.28 H
2. Convert the following binary numbers to decimal and hexadecimal
(1) 111010 B=58 =3A H (2) 1011 1100.111B= 188.875= BC.E H (3) 0.11011B=0.84375 =0.D8H (4) 1110.01 B=30.25 =1E.4H
3. Complete the addition and subtraction of the following binary numbers
(1) 1001.11 + 100.01= 1110.00 (2) 1101010110.1001-0100001.0011=01110101.0110 (3) 00111101 + 10111011=11111000 (4) 01011101.0110- 101101.1011= 101111.1011
4. Complete the addition and subtraction of the following hexadecimal numbers
(1) 745CH+ 56DFH= D14B H (2) ABF.8H one EF6.AH=9C28.E H (3) 12AB.F7+ 3CD.05=1678.FC H (4) 6F01H- EFD8H= = 7F29 H
5. Calculate the value of the following expression
(1) 128.8125 + 10110101.1011B + 1F.2H= 101010101.1010B (2) 287.68 I 10101010.11H+ 8E.EH= 103.CEH (3) 18.9 + 1010.1101B + 12.6H I 1011.1001= 36.525
6. When the word length n is 8 bits and 16 bits, find the complement of the following decimal numbers.
(1) X=-33 Complement of:1101 1111, 111111111011111 (2) Y=+ 33 Complement of: 0010 0001, 0000 0000 0010 0001 (3) Z=- 128 Complement of: 1000 0000， 1111 1111 1000 0000 (4) N=+127 Complement of: 0111 1111， 0000 00000111 111 (5) A=- 65 Complement of: 1011 111， 111 111 1011 111 (6) B=+ 65 Complement of: 0100 0001，0000 0000 0100 0001 (7) C=A complement of 96: 10100000， 111 111 1010 0000 (8) D= +96 Complement of: 01 10 0000，0000 0000 0110 0000
7. Write the true values of the following binary numbers represented by complements
(1) [X]repair= 1000 0000 0000 0000H X=I. 10 million H=I 32768 (2) [Y]repair=0000 0001 0000 0001 H Y=+0000000100000001H=Ten 257 (3) [Z]repair=1111 1110 10100101 H Z=I 0000001 0101 1011 H=I. 347 (4) [A]repair =000000100101 0111 H A= +000000100101 0111 H=Ten 599
8. Set the machine word length as 8 bits and the highest bit as symbol bit. Try to perform binary complement operation on the following formats and judge whether the result overflows.
(1) 43+8 33H(No overflow) (2)-52+7 D3 H(No overflow) (3) 60+90 96H(overflow) (4)72-8 40H(No overflow) (5) -33+(-37) 0BAH (No overflow) (6)-90+(-70) 60 H(overflow) (7) -9-(I 7) FE H(No overflow) (8) 60-90 E2 H(No overflow)
9. Set variables X = 11101111B, y = 11001001B, z = 01110010B, v = 01011010B, and try to calculate x+y =?, x+z＝?， y+z＝?， z+v＝?
Excuse me?
① If it is an unsigned number, is the calculation result correct? incorrect incorrect Incorrect ② If it is a signed complement, does the calculation result overflow? No overflow no overflow no overflow overflow
12. Try to calculate the values represented by the following binary numbers when they are unsigned number, original code, inverse code, complement code and 8421BCD code.
If it is a non 8421BCD number, please indicate.
(1) 10001000B Unsigned number: 27+23= 136 Original code: - 000 1000=-8 Inverse code: - 1110111=-119 Complement:- 111 1000=- 120 8421BCD code: 88 8421BCD code:Non 8421 BCD code (2) 00101001B Unsigned number: 25+23+ 20 =41 Original code: 41 Inverse code: 4 Complement: 4 8421BCD code: 29 (3) 11001001B Unsigned number: 27+26+ 23+20 = 201 Original code: - 100 1001 =- 73 Inverse code: -011 0110=- 54 Complement: -0110111=- 55 (4) 10010011B Unsigned number: 27+24+ 21+20= 147 Original code: - 001 0011=- 19 Inverse code: - 110 1100=- 108 Complement: - 1101101 =- 109
Chapter 3: 80x86 microprocessor
1. Briefly describe the functions of BIU and EU in 8086 / 8088 CPU, and explain their parallel working process.
(1) BIU Function: calculate the 20 bit physical address and complete it CPU With memory or I/O Data transfer between ports.
(2) EU Function: execute instructions and BIU Provide the required valid address.
(3) Parallel working process: when EU When an instruction is taken from the instruction queue for execution, BIU The instruction fetched from memory is added to the instruction queue. In this way, the parallel work of fetching and executing instructions is realized.
2. What registers are there in the 8086 / 8088 CPU? What is its main function?
Answer:
8086／8088CPU There are 14 internal registers, which can be divided into 4 categories: 4 data registers, 4 address registers, 4 segment registers and 2 control registers. Its main functions are:
(1) Data registers: generally used to store data, but each has its own specific purpose.
AX(Accumulator)It is called an accumulator. Using the register to store the operation results can simplify the instruction and improve the execution speed of the instruction.
In addition, all I／O Instructions use this register to exchange information with peripheral ports.
BX(Base)It is called a base register. Used to store the offset address of the operand in the data segment in memory,
CX(Counter)Called a counter. When designing a cyclic program, using this register to store the number of cycles can simplify the program instructions and improve the running speed of the program.
DX(Data)It is called a data register. Register indirectly addressed I／O Stored in instruction I／O Port address;
When doing double word length multiplication and division, DX And AX Store a double word operand together, where DX Store 16 digits high.
(2) Address register: generally used to store the offset address in the segment.
SP(Stack Pointer)Called stack pointer register. When using stack operation instructions(PUSH or POP)When operating on the stack, the system will automatically SP Content of
Subtract 2 or add 2 so that it always points to the top of the stack.
BP(Base Pointer)It is called a base register. As a general-purpose register, it can be used to store data, but more often and more important is to store the offset address of the operand in the stack segment.
SI(Source Index)It is called the source index register. SI Store the offset address of the source string in the data segment.
DI(Destination Index)It is called destination index register. DI Store the offset address of the destination string in the additional data segment.
(3) Segment register: used to store segment addresses
CS(Code Segment)Called a code segment register, it is used to store the segment address of the code segment currently used by the program.
CS The contents of the are shifted to the left by 4 bits plus the instruction pointer register IP The content of is the physical address of the next instruction to be read in memory.
DS(Data Segment)Called segment register, it is used to store the segment address of the data segment currently used by the program.
DS The physical address for reading and writing the specified unit of the data segment is obtained by shifting the content of the data segment by 4 bits to the left and adding the offset address given according to the memory addressing mode in the instruction.
SS(Stack Segment)Called stack segment register, it is used to store the segment address of the stack segment currently used by the program.
Stack is a special storage area developed in memory and organized according to the principle of "first in and last out". It is mainly used to protect breakpoints and site when calling subroutines or executing interrupt service programs.
ES(Extra Segment)Called additional data segment register, it is used to store the segment address of the additional data segment currently used by the program. The additional data segment is used to store the destination string of string operation.
(4) Control register
IP(Instmcdon Pointer)Called instruction pointer register, it is used to store the offset address of the next instruction to be read in the code segment. User programs cannot be accessed directly IP.
FLAGS It is called flag register. It is a 16 bit register, but only 9 bits are used. These 9 bits include(Two status flag bits and three control flag bits.
It is used to reflect some characteristics of the results of arithmetic and logic operations, or to control CPU Some kind of operation.
3. What registers in 8086 / 8088 CPU can be used to indicate the offset address of operands in a certain section of memory?
A: there are 6 registers that can be used to indicate the offset address in the segment: IP,SP,BP,BX,SI,DI
4. What are the flag bits of flag register FLAGS in 8086 / 8088 CPU? What are their meanings and functions?
A: there are 9 flags in the flag register, which are divided into two categories: 6 status flags and 3 control flags. Its functions are:
(1) Status flag: used to reflect some characteristics of arithmetic and logical operation results.
CF(Carry Flag)—Carry flag bit. When performing addition and subtraction, if carry or borrow occurs in the highest bit, then CF Is 1, otherwise 0.
This flag bit is usually used to judge whether the operation result of unsigned number exceeds the range of unsigned number that can be represented by the computer.
PF(Parity Flag)—Parity flag bit. When the lower 8 bits of the instruction execution result contain an even number of 1,PF Is 1, otherwise 0.
AF(Auxiliary Flag)—Auxiliary carry flag bit. When an addition or subtraction instruction is executed, if there is carry or borrow from the lower 4 bits to the upper 4 bits of the lower byte of the result, then AF Is 1, otherwise 0.
ZF(Zero Flag)—Zero flag bit. If the current operation result is 0, then ZF Is 1, otherwise it is 00
SF(Sign Flag)—Symbol flag bit. When the highest bit of the operation result is 1, SF=1，Otherwise 00
OF(Overflow Flag)—Overflow flag bit. When the operation result exceeds the numerical range that can be represented by the signed number, that is, overflow, OF=1，Otherwise, it is 0.
This flag bit is usually used to determine whether the signed number operation result overflows o
(2) Control flag bit: used to control CPU The operation is set or cleared by the program. They are:
TF(TrapFlag)—track(trap)Flag bit. It is set for the convenience of the test program. If will TF Set 18086／8088CPU In single step mode, otherwise, the program will be executed normally.
IP(Interrupt Flag)—Interrupt enable flag bit. It is a control flag bit used to control maskable interrupts.
If used STI Instruction will IF Set to 1 to allow CPU Accept external slave INTR Maskable interrupt request signal sent from pin; If used CLI Instruction will IP If 0 is cleared, it is prohibited CPU Accept maskable interrupt request signal. IF
The status of has no effect on unshielded interrupts and internal interrupts.
DF(DirectionFlag)—Direction flag bit. If used STD take DF Set to 1, the string operation is performed by subtracting the address, that is, starting from the high address, the address decreases automatically each time;
If used CLD take DF When 0 is cleared, the string operation is carried out by increasing the address, that is, the address is automatically incremented every operation.
5. How many bits does the address bus of 8086 / 8088 CPU have? What is the addressing range?
Answer: 8086/8088 There are 20 address buses and the addressing range is 1 MB
6. What is instruction queue? What is the function of instruction queue in 8086 / 8088 CPU? What are their lengths?
(1) Instruction queue: the buffer that stores pre executed instructions in order is called instruction queue based on the "first in first out" principle.
(2) Function of instruction queue: storage EU The instruction to be executed so that CPU The fetching and executing instructions can work in parallel.
(3) Length of instruction queue: 6 bytes for 8086 and 4 bytes for 8088.
7. What is the difference between Intel 8086 and 8088?
A: there are three differences between 8086 and 8088:
(1) The number of bits of the external data bus is different (i.e. address)／Data time-sharing multiplexing (different number of pins);
8086 Is 16 bits: AD15～AD0 .
8088 Is 8 bits: AD7～AD0 .
(2) The length of internal instruction queue buffer is different;
8086 There are 6 bytes. When two empty bytes appear in the instruction queue, BIU Will be taken to supplement.
8086 There are 4 bytes. When an empty byte appears in the instruction queue, BIU Will be taken to supplement.
(3) Some external control buses have different definitions.
① 8086 Pin 28 of is defined as M／IO(S2)，8088 Defined as IO／M(S2)
② 8086 Pin 34 of is defined as BHE／S7，8088 Defined as SS0／(HIGH)
8. Briefly describe the working principle of 8086 CPU using address latch signal ALE to separate address A15 ~ A0 from data D15 ~ D0.
In any bus cycle T1 Status, ALE Are high to indicate the current address／The address information is output on the data multiplexing line, stay ALE The falling edge from high to low loads the address into the address latch, and T2,T3 and T4 Status, ALE Low level, To represent the current address／The output on the data multiplexing line is data information, which is transmitted through the data transceiver.
9. What is a logical address? What is a physical address? If the known logical address is BA00:A800, try to find the physical address.
Logical address: the storage unit address represented by segment address and offset address is called logical address.
Physical address: CPU The 20 bit address actually used when accessing the memory is called the physical address.
If the logical address is BA00H:A800H
Physical address＝BA00H×10H＋A800H＝C4800H
10. Briefly describe the function of stack pointer register SP and the operation process of stack.
(1) SP Function: indicates the offset address during stack in and stack out operations. (2) Stack operation process: when entering the stack, first SP－2，Then push the data into the stack (i.e. move first and then in); When out of the stack, first pop the data out of the stack, and then SP+2(First out then move).
Chapter 4: 80x86 instruction set
Chapter IV 80X86 instruction system
1. Indicate the addressing mode of the source operand
⑴ MOV BX，2000H ；Immediate Addressing ⑵ MOV BX，[2000H] ；Direct addressing ⑶ MOV BX，［SI］ ；register indirect addressing ⑷ MOV BX，[SI＋2000H] ；Register Relative Addressing ⑸ MOV [BX＋SI]，AL ；Register addressing ⑹ ADD AX，[BX＋DI＋80] ；Base index relative addressing ⑺ MUL BL ；Register addressing ⑻ JMP BX ；Intrasegment indirect addressing ⑼ IN AL，DX ；Port indirection ⑽ INC WORD PTR [BP+10H] ；Register Relative Addressing ⑾ MOV CL,LENGTH VAR ；Immediate Addressing ⑿ MOV BL，OFFSET VAR1 ；Immediate Addressing
-
Indicate whether the following instructions are correct
(1) MOV DS，0100H ；Wrong. When the source operand is an immediate, the destination operand cannot be a period register (2) MOV BP，AL ；Wrong. Inconsistent operand types (3) XCHG AH，AL ；correct. (4) OUT 310H，AL ；Wrong. The range of port direct addressing should be 0～FFH between (5) MOV BX，[BX] ；correct. (6) MOV ES:[BX＋DI] ，AX ；correct. (7) MOV AX，[SI＋DI] ；Wrong. A valid address in memory addressing cannot consist of two index registers (8) MOV SS:[BX+SI+100H],BX ；correct. (9) AND AX，BL ；Wrong. Inconsistent operand types (10) MOV DX，DS:[BP] ；correct. (11) ADD [SI]，20H ；Wrong. use PTR Description type (12) MOV 30H，AL ；Wrong. Destination operand cannot be immediate (13) PUSH 2000H ；Wrong. The operand of a stack instruction cannot be an immediate (14) MOV [SI]，[2000H] ；Wrong. Two operands cannot be memory operands at the same time (15) MOV SI，AL ；Wrong. Inconsistent operand types (16) ADD [2000H]，20H ；Wrong. use PTR Description type (17) MOV CS，AX ；Wrong. The destination operand cannot be a code segment register (18) INC [DI] ；Wrong. need PTR Description type (19) OUT BX，AL ；Wrong. Port indirection registers can only be DX register (20) SHL BX，3 ；Wrong. It should be used when the number of shifts is greater than 1 CL register (21) XCHG CX，DS ；Wrong. Segment registers cannot appear in swap instructions (22) POP AL ；Wrong. The operand of a stack instruction can only be a word operand(That is, 16 bit operands)
Write out the calculation expression of the physical address of the memory operand
(1) MOV AL，[DI] ；(DS)×10H＋(DI) (2) MOV AX，[BX+SI] ；(DS)×10H＋(BX)＋(SI) (3) MOV 5[BX+DI]，AL ；(DS)×10H＋(BX)＋(DI)＋5 (4) ADD AL，ES:[BX] ；(ES)×10H＋(BX) (5) SUB AX，[1000H] ；(DS)×10H＋1000H (6) ADC AX，[BX+DI+2000H] ；(DS)×10H＋(BX)＋(DI)＋2000H (7) MOV CX，[BP+SI] ；(SS)×10H＋(BP)＋(SI) (8) INC BYTE PTR [DI] ；(DS)×10H＋(DI)
If (DS) = 3000H, (BX) = 2000H, (SI) = 0100H, (ES) = 4000H, calculate the physical address of the following memory operands.
(1) (DS)×10H＋(BX)＝3000H×10H＋2000H＝32000H (2) (DS)×10H＋(BX)＋(SI)＋1000H＝3000H×10H＋2000H＋0100H＋1000H＝33100 H (3) (DS)×10H＋(BX)＋(SI)＝3000H×10H＋2000H＋0100H＝32100 H (4) (ES)×10H＋(BX)＝4000H×10H＋2000H＝42000 H
5. If (CS) = E000H, describe the range of addressable physical storage space of the code segment.
∵ The minimum physical address is:(CS)×10H＋0000H＝E0000H The maximum physical address is:(CS)×10H＋FFFFH＝EFFFFH ∴ The range of code segment addressable physical storage space is: E0000H～EFFFFH
6. Set (SP) = 2000H, (AX) = 3000H, (BX) = 5000H, after executing the following program segments, (SP) =?, (AX)＝?， (BX)＝?
PUSH AX
PUSH BX
POP AX
(SP)＝1FFEH，(AX)＝5000H， (BX)＝5000H
7. Try to compare the similarities and differences between SUB AL, 09H and CMP AL, 09H. If (AL)=08H, after executing the above two instructions respectively, (AL) =?, CF=?， OF=0，ZF=?
(1) Same point: both instructions can be completed(AL)－09H And all affect the six status flag bits;
difference: SUB Instruction returns the result of the operation to AL Register, and CMP Command does not return.
(2) SUB AL，09H ；(AL)=FFH，CF=1，OF=0，ZF=0
CMP AL，09H ；(AL)=08H，CF=1，OF=0，ZF=0
8. Execute the following instructions respectively to try to find the content of AL and the status of each status flag bit.
(1) MOV AL，19H ；
ADD AL，61H ；
(AL)=7AH OF=0 SF=0 ZF=0 AF=0 PF=0 CF=0
(2) MOV AL，19H ；
SUB AL，61H ；
(AL)=B8H OF=0 SF=1 ZF=0 AF=0 PF=1 CF=1
(3) MOV AL，5DH ；
ADD AL，0C6H ；
(AL)=23H OF=0 SF=0 ZF=0 AF=1 PF=0 CF=1
(4) MOV AL，7EH ；
SUB AL，95H ；
(AL)=E9H OF=1 SF=1 ZF=0 AF=0 PF=0 CF=1
9. Achieve the following required functions with the least instructions.
(1) AH The upper 4 bits of are cleared.
AND AH，0FH
(2) AL The top 4 digits of the are reversed.
XOR AH, 0F0H
(3) AL The high 4 bit of the is shifted to the low 4 bit, and the high 4 bit is cleared to 0.
MOV CL，4
SHR AL，CL
(4) AL The low 4 bit of is shifted to the high 4 bit, and the low 4 bit is cleared to 0.
MOV CL，4
SHL AL，CL
10. Let (BX) = 6D16H, (AX) = 1100H, write out the contents of ax and BX registers after the execution of the following three instructions.
MOV CL，06H
ROL AX，CL
SHR BX，CL
(AX)=4004 H (BX)=01B4 H
11. Set the initial value (AX) = 0119H, and after executing the following program segments, (AX) =?
MOV CH，AH
ADD AL，AH
DAA
XCHG AL，CH
ADC AL，34H
DAA
MOV AH，AL
MOV AL，CH (AX)=3520 H
12. Indicate the functions of the following program segments.
(1) MOV CX，10
LEA SI，First
LEA DI，Second
REP MOVSB take First The first 10 characters in the string are transferred to Second in
(2) CLD
LEA DI，[0404H]
MOV CX，0080H
XOR AX，AX
REP STOSW Set the starting address to 0404 H Start 80 H Units set to 0
13. Let (BX) = 6F30H, (BP) = 0200H, (SI) = 0046H, (SS) = 2F00H, (2f246h) = 4154H, try to execute XCHG BX, (BX) = after [BP + Si]?, (2F246H)＝?
(BX)＝4154H (2F246H)＝6F30H
14. Set (BX) = 0400H, (DI) = 003CH, execute LEA BX, [BX + Di + 0F62H], (BX) =?
(BX)＝139E H
15. Let (DS) = C000H, (C0010H) = 0180H, (C0012H) = 2000H, after executing LDS SI, [10H], (SI) =?, (DS)＝?
(SI)＝0180 H，(DS)＝2000 H
16. It is known that (DS) = 091DH, (SS) = 1E4AH, (AX) = 1234H, (BX) = 0024H, (CX) = 5678H, (BP) = 0024H, (SI) = 0012H, (DI) = 0032H, (09226H) = 00F6H, (09228H) = 1E40H. Try to find the result after executing the following instructions separately.
(1) MOV CL，20H[BX][SI] ；(CL)＝0F6 H
(2) MOV [BP][DI]，CX ；(1E4F6 H)＝5678 H
(3) LEA BX，20H[BX][SI] ；(BX)=0056 H
MOV AX,2[BX] ；(AX)=1E40 H
(4) LDS SI,[BP][DI] ；
MOV [SI]，BX ；((SI))=0024 H
(5) XCHG CX，32H[BX] ；
XCHG 20H[BX][SI]，AX ；(AX)＝5678 H ，(09226H)＝1234 H
17. If the registers and ram parameters in the CPU are as shown in the figure, try to find out the contents of the corresponding registers and storage units of the CPU and RAM after independently executing the following instructions?
(1)MOV DX，[BX+2] ；(DX)=0006H，(BX)=0004H
(2)PUSH CX ；(SP)=0FFEH
(3)MOV CX，BX ；(CX)=0004H，(BX)=0004H
(4)TEST AX，01 ；(AX)=8094H，(CF)=0
(5)MOV AL，[SI] ；(AL)=87H
(6)ADC AL，[DI] ；(AL)=0CCH，(CF)=0
DAA ；(AL)=32H
(7)INC SI ；(SI)=0009H
(8)DEC DI ；(DI)=0009H
(9)MOV [DI]，AL ；((DI))=94H
(10)XCHG AX，DX ；(AX)=17C6H，(DX)=8094H
(11)XOR AH，BL ；(AH)=84H，(BL)=04H
(12)JMP DX ；(IP)=17C6H
18. (DS) = 2000H, (BX) = 1256H, (SI) = 528FH, offset = 20A1H, (232F7H) = 3280H, (264E5H) = 2450H, try to find the result after executing the following instructions.
(1) JMP BX ；(IP)＝1256 H (2) JMP TABLE[BX] ；(IP)＝3280 H (3) JMP [BX][SI] ；(IP)＝2450 H
20. Let (IP) = 3D8FH, (CS) = 4050H, (SP) = 0F17H, and try to point out the contents of (IP), (CS), (SP), ((SP)), ((SP) + 1), ((SP) + 2) and ((SP) + 3) after executing CALL 2000H:0094H.
CALL The instruction is a 5-byte instruction, and the address of the next instruction is 4050 H: 3D94H So after execution
(IP)＝0094H，(CS)＝2000H,(SP)＝0F13H
((SP))＝94H，((SP)＋1)＝00H，((SP)＋2)＝00H，((SP)＋3)＝20H
Chapter 5: assembly programming language
2.PLENTH The value of is 0022, which represents the currently allocated cell space; 3.L The value of is 6; 5.(AX)=000AH；(BL)=0AH；(CL)=01H； 10. MOV AX, 4A82H MOV DL，AH AND DL，0F0H MOV CL，4 SHR DL，CL PUSH AX AND AH，0FH MOV BH，AH AND AL，0F0H MOV BL，AL MOV CL，4 SHR BL，CL MOV CL，BH POP AX AND AL，0FH
data segment
string1 db 'I am a student.'
string2 db 'I am a student .'
yes db 'match',0dh,0ah,'$'
no db 'no match',0dh,0ah,'$'
data ends
code segment
assume cs:code,ds:data,es:data
start: push ds
sub ax,ax
push ax
mov ax,data
mov ds,ax
mov es,ax
lea si,string1
lea di,string2
mov cx,string2-string1
cld
repe cmpsb
jnz dispno
mov ah,9
lea dx,yes
int 21h
jmp exit
dispno: mov ah,9
lea dx,no
int 21h
exit: MOV AH,4CH
INT 21H
code ends
13
DATA SEGMENT
M DB 11H,22H,33H,44H,64H,87H,34,29,67H,88H,0F6H
DB 43H,0B7H,96H,0A3H,233,56H,23H,56H,89H
C EQU 20
P DB 20 DUP(?)
N DB 20 DUP(?)
PLUS DB 'PLUS',0DH,0AH,'$'
MINUS DB 'MINUS',0DH,0AH,'$'
J DB 2 DUP(?)
DATA ENDS
CODE SEGMENT
ASSUME CS:CODE, DS:DATA
START: MOV AX,DATA
MOV DS,AX
LEA SI,M
LEA DI,P
LEA BX,N
MOV CX,C
MOV DX,0
LOOP1: LODSB
TEST AL,80H
JNZ MINUS1 ;Negative transfer
MOV [DI],AL
INC DI
INC DH ;Positive number
JMP AGAIN
MINUS1: MOV [BX],AL
INC BX
INC DL ;Save negative number
AGAIN: DEC CX
JNZ LOOP1
MOV WORD PTR J,DX ;Save results
MOV DX,OFFSET MINUS
MOV AH,9
INT 21H ;Display prompt information
MOV BL,J
MOV CH,2
ROTATE: MOV CL,4
ROL BL,CL
MOV AL,BL
AND AL,0FH
ADD AL,30H
CMP AL,3AH
JL POR
ADD AL,7
POR: MOV DL,AL
MOV AH,2
INT 21H
DEC CH
JNZ ROTATE ;Output negative numbers in hexadecimal form
MOV AH,2
MOV DL,0DH
INT 21H
MOV DL,0AH
INT 21H
MOV DX,OFFSET PLUS
MOV AH,9
INT 21H
MOV DH,J+1
MOV CH,2
ROTATE1: MOV CL,4
ROL DH,CL
MOV AL,DH
AND AL,0FH
ADD AL,30H
CMP AL,3AH
JL POR1
ADD AL,7
POR1: MOV DL,AL
MOV AH,2
INT 21H
DEC CH
JNZ ROTATE1
MOV AH,4CH
INT 21H
CODE ENDS
END START
Chapter 6: semiconductor memory
2. (1) there are 10 on-chip addressing lines and 6 inter chip addressing lines in 64 chips
(2) 128 There are 11 intra chip addressing lines and 5 inter chip addressing lines (3) 16 There are 11 intra chip addressing lines and 5 inter chip addressing lines (4) 2 There are 14 intra chip addressing lines and 2 inter chip addressing lines
3,1024 × 8 RAM chip and 11 address lines. 8 data lines
6. Known: 8-bit microcomputer address, 16 bit bus, 12KB memory system is designed, in which ROM occupies 8KB from 0000H and RAM occupies 4KB from 2000H. INTEL 2716 and 2114 are selected as memory chips respectively
The analysis is as follows: (1) ROM 2716 2K×8 Chip, 4 chips, word expansion, 11 on-chip addressing lines RAM 2114 1K×4 8 chips are required for word bit expansion and 10 on-chip addressing lines (2)Address range: A15 A14 A13 A12 A11 A10 ROM1: 0000H~07FFH 0 0 0 0 0 0 ROM2: 0800H~0FFFH 0 0 0 0 1 0 A15 A14 A13 A12 A11 A10 ROM3: 1000H~17FFH 0 0 0 1 0 0 ROM4: 1800H~1FFFH 0 0 0 1 1 0 RAM1,2: 2000H~23FFH 0 0 1 0 0 0 RAM3,4: 2400H~27FFH 0 0 1 0 0 1 RAM5,6: 2800H~2BFFH 0 0 1 0 1 0 RAM7,8: 2C00H~2FFFH 0 0 1 0 1 1
(3) A11, A12, A13 3:8 decoder decoding input (primary decoding)
ROM1 : Y0 ROM2 : Y1 ROM3 : Y2 ROM4 : Y3 RAM1,2 : Y4 And A10 (Two stage decoding) RAM3,4 : Y4 And A10 RAM5,6 : Y5 And A10 RAM7,8 : Y5 And A10
(4) Sketch connection
9. A small computer system composed of 8088, 32KB ROM, the address range is 00000 ~ 07fffh, the RAM occupies 8KB, and the address range is 0800h ~ 09fffh. ROM selection 2764 (8K) × 8) 2114 (1K) RAM is selected × 4)
The analysis is as follows (1) ROM 2764 8K×8 Chip, 4 chips, word expansion, 13 on-chip addressing lines RAM 2114 1K×4 The chip needs 16 chips, word bit expansion, and 10 on-chip addressing lines (2) Address range: A15 A14 A13 A12 A11 A10 ROM1 00000~01FFF H 0 0 0 (Primary decoding) ROM2 02000~03FFF H 0 0 1 ROM3 04000~05FFF H 0 1 0 ROM4 06000~07FFFH 0 1 1 RAM1(group)08000~083FFH 1 0 0 0 0 0 (Two stage decoding) RAM2 08400~087FFH 1 0 0 0 0 1 RAM3 08800~08BFFH 1 0 0 0 1 0 RAM4 08C00~08FFFH 1 0 0 0 1 1 RAM5 09000~093FFH 1 0 0 1 0 0 RAM6 09400~09FFFH 1 0 0 1 0 1 RAM7 09800~09BFFH 1 0 0 1 1 0 RAM8 09C00~09FFFH 1 0 0 1 1 1
(3) ROM1 Y0 (1 # decoder A15 A14 A13 decoding input)
ROM2 Y1 ROM3 Y2 ROM4 Y3 RAM1 Y0 (2 # decoder A12 A11 A10 Decoding input 1 # Y4 Do 2#Control signal of) RAM2 Y1 RAM3 Y2 RAM4 Y3 RAM5 Y4 RAM6 Y5 RAM7 Y6 RAM8 Y7
(4) Two 3:8 decoders are required
Chapter 7: input / output and interrupt
Chapter 8: programmable interface chip and its application
The answers you didn't write will be added later